1. Field of the Invention
The present invention relates to a serializer and a method of serializing parallel data into a serial data stream, and more particularly to a serializer and a method of serializing parallel data into a serial data stream, which reduces or prevents the jitter of a serialized output signal in high speed and/or low voltage applications.
2. Description of the Related Art
FIG. 1 is a circuit diagram showing a conventional 2:1 serializer 100. The conventional 2:1 serializer 100 includes a first pull-up section 10, a second pull-up section 14, a first pull-down section 12 and a second pull-down section 16. The first pull-up section 10 includes two PMOS transistors P1 and P2, the second pull-up section 14 includes two PMOS transistors P3 and P4, the first pull-down section 12 includes two NMOS transistors N1 and N2, and the second pull-down section 16 includes two NMOS transistors N3 and N4.
The conventional 2:1 serializer 100 receives a first power voltage VDD, a second power voltage VSS, two parallel data signals D0 and D1 and clock signals CK0 and Ck1, and serializes the parallel data signals D0 and D1 and outputs a serialized data stream via an output terminal OUTB. The first power voltage VDD is a positive voltage level. The second power voltage VSS may have an earth potential or a negative voltage level.
As shown in FIG. 1, when clock signal CK0 has a high level and clock signal CK1 has a low level, PMOS transistor P4 and NMOS transistor N1 are turned on and PMOS transistor P2 and NMOS transistor N3 are turned off. Thus, the second power voltage VSS is outputted to the output terminal OUTB when the data D1 has a high level.
When clock signal CK0 has a low level and clock signal CK1 has a high level, PMOS transistor P2 and NMOS transistor N3 are turned on and PMOS transistor P4 and NMOS transistor N1 are turned off. Thus, the first power voltage VDD is outputted to the output terminal OUTB when the data D0 has a high level and the serialized output signal swings between the first and second power voltage VDD and VSS.
According to the conventional serializer 100, gate-source parasitic capacitance Cgs, a gate-drain parasitic capacitance Cgd and a source-substrate parasitic capacitance Csb may exist at the node Da, Db, Dc and Dd. Thus, a coupling effect is induced. As a result, jitter is generated due to inter symbol interference (ISI) between the input signals (CK0, CK1, D0, D1) and the output signal. Jitter is likely to be generated due to inter symbol interference (ISI) because of the full swing of the output signal between the first and second power voltages, VDD and VSS.
In another conventional serializer, the serializer is connected to a large output driver transistor and the serializer requires an additional bias circuit for maintaining a voltage level of a voltage signal inputted to the output driver transistor to a special voltage level to reduce or prevent fluctuations in the voltage level of the voltage signal. Thus, the serializer requires an increased semiconductor chip area due to the additional circuitry.
In yet another conventional serializer, when data and clock signals are input to the serializer, the voltage output at floating nodes of serially connected NMOS transistors affects an output signal of the serializer, and jitter may again be induced. In addition, a load of PMOS transistor is turned on always even during power down status and the serializer consumes a lot of power.